1. Field of the Invention
The present invention relates to circuits for testing a memory, in particular a Random-Access Memory (RAM) in a microprocessor system.
2. Discussion of the Related Art
For testing a memory, there are several methods for detecting different types of abnormal situations, such as memory cells stuck at a determined value, shorted or open address or data lines, etc. By testing a memory using several methods and by adequately analyzing the results, an exhaustive memory test can be performed, thus allowing localisation of all abnormal situations. Test methods are described in IEEE Transactions on Computers, Vol. C-27, No. 6, June 1978, "Efficient Algorithms for Testing Semiconductor Random-Access Memories". In this document, various works on test methods are referred to.
FIG. 1 schematically represents a conventional microprocessor system. Such system includes a Central Processing Unit (CPU) 1, a Read-Only Memory (ROM) 2, a Random-Access Memory (RAM) 3, and a Direct Memory Access (DMA) controller 4, that are connected to a microprocessor bus comprised, for example, of a 16-line data bus D, and a 24-line address bus A.
Conventionally, in order to test the RAM 3, microprocessor 1 executes a test program whose instructions are stored in ROM 2. This test program is executed, for example, at power on of the system, or at regular time intervals.
When testing the RAM 3, microprocessor 1 generally executes, for each cell of the RAM to be tested, at least one write and one read in the RAM together with several instruction reads from ROM. During a memory test, a large number of accesses are made to ROM, which causes the test to be substantially slowed down because accesses in ROM are particularly time consuming.
In practice, an exhaustive test of a 2-megabyte RAM, which is a common value, lasts for approximately four hours; during this period, the microprocessor cannot be used to perform other tasks. Hence, such a test is executed as seldom as possible.
Additionally, a program that executes an exhaustive memory test occupies approximately 20 kilobytes, which is a substantial value involving non-negligible extra cost in mass produced microprocessor systems.
In order to accelerate test programs, one could envisage storing the instructions of the test program in a battery backed-up RAM. However, such an approach is expensive and much time would still be spent on the numerous instruction reads.
It would also be possible to test memories without resorting to a test program but by using a hard wired system in the form of a specific test circuit connected to the microprocessor bus. However, it is not desirable to provide an additional integrated test circuit that has to be inserted on a microprocessor board, because such a solution would involve extra costs for mounting and designing microprocessor boards.